Field of Invention
Various exemplary embodiments of the present invention relate generally to a semiconductor device and, more particularly, to a semiconductor memory device and a method of fabricating the same.
Description of Related Art
With the rapid development of semiconductor memory devices, such as non-volatile memory devices, there is an increased demand for higher degrees of integration. Conventional semiconductor memory devices, which include memory cells arranged two-dimensionally in a given area, increase the degree of integration by reducing the size of the memory cells. However, there are physical limits to how far the size of memory cells may be reduced. To overcome these physical limits, a semiconductor memory device having memory cells that are arranged three-dimensionally over a semiconductor substrate has been proposed. By arranging memory cells in three-dimensions, the area of a semiconductor memory device may be used more efficiently. In addition, the degree of integration of semiconductor memory devices having three-dimensionally arranged memory cells may be greater than that of semiconductor memory devices having two-dimensionally arranged memory cells. For example, when memory strings of a NAND flash memory device are arranged three-dimensionally, the NAND flash memory device may maximize its degree of integration. Therefore, three-dimensional semiconductor memory device technology is constantly under development.
A three-dimensional semiconductor memory device may include word lines stacked over a substrate at predetermined spacings/intervals, a channel layer passing through the word lines in a vertical direction relative to the substrate, a tunnel insulating layer surrounding the channel layer, a charge storage layer surrounding the tunnel insulating layer, and a blocking insulating layer surrounding the charge storage layer. Memory cells of the three-dimensional semiconductor memory device may store data by trapping charges in a portion of the charge storage layer arranged at an intersection between the word lines and the channel layer.